Statement of Purpose

I'm launching a blog today. It's spring break and I've got nothing better to do for a couple days (aside from computer architecture lab) and I've been kicking this idea around in the back of my head for a few weeks so I figure I'll give it a shot.

Basically this blog is meant to provide tips and tricks for leaning Verilog and SystemVerilog. When I first starting learning Verilog in a course called "Structure and Design of Digital Systems" (course no. 18-240 at CMU), I remember being pretty confused by certain aspects of Verilog. For example, "reg". To those who know, need I say more?

To those who don't yet but want to, this blog is for you. Hopefully the things I have to say will save you some of the pain and misery I endured. Then again, some see that as a right-of-passage.

Perhaps with time I might expand this blog to include more than simply Verilog and SystemVerilog. I might occasionally post things about other topics in electrical and computer engineering, code-related or otherwise.

Oh yeah, and a little disclaimer: I'm a junior undergrad student which means I'm no expert and potentially everything I say or piece of advice I give here could be totally wrong, stupid, and all-around lousy. Read at your own risk.

And remember, always_comb your hair!

Paul Mueller Kennedy